Design Verification Engineer (Einfochips)

Position: Design Verification Engineer (Einfochips) Job Description: Experience: 6 Years Location: San Jose CA Job Description: What candidate will Be Doing: At-least 6 years of experience in System Verilog HVL and C++/C At-least 6 year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, …